Method for producing micromechanic sensors and sensors produced by said method

ABSTRACT

Proposed is a method for manufacturing micromechanical sensors and sensors manufactured by this method, where openings ( 2 ) are introduced into a semiconductor substrate ( 1 ). After the openings ( 2 ) are introduced into the semiconductor substrate ( 1 ), a subsequent temperature treatment is carried out, in which the openings ( 2 ) are converted into voids in the depth of the substrate ( 1 ).

BACKGROUND INFORMATION

[0001] The present invention starts out from a method for manufacturingmicromechanical sensors and micromechanical sensors produced by it,according to the definition of the species in the independent claims. Anarticle of Mizushima et al., Applied Physics Letter, Vol. 77, No. 20,Nov. 13, 2000, page 3290 ff., already describes a method, in which voidsare produced in the semiconductor substrate by introducing openings andcarrying out a subsequent temperature treatment. However, thesestructures are only intended to be used in integrated circuits. Amultitude of other manufacturing processes, in particular the so-calledsacrificial-layer technique, are known for manufacturing sensors. Inthis context, a silicon layer is produced on a sacrificial layer. Thesacrificial layer is then removed again after the silicon layer ispatterned.

SUMMARY OF THE INVENTION

[0002] The method of the present invention possessing the features ofthe independent claim has the advantage over the background art, that aparticularly simple method for manufacturing micromechanical sensors isspecified. In this context, the micromechanical sensors constitutesensor elements, which are made of monocrystalline silicon. The methodis also suitable for the integration of circuit elements.

[0003] Further advantages and improvements are yielded by the featuresof the dependent claims. In order to ensure that a void is reliablyproduced, the introduced openings should be deeper than the diameter.They should preferably have a diameter of less than 1 μm and be deeperthan 2 μm. Sufficiently high temperatures ensure that the mobility ofthe silicon atoms on the substrate is sufficient. The actual sensorelements are then formed by further processing steps. In this context,the deposition of an epitaxy layer and the introduction of dopants areadvantageous.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Exemplary embodiments of the present invention are shown in thedrawings and are explained in detail in the following description. Thefigures show:

[0005]FIGS. 1 through 4 a first process sequence, and

[0006]FIGS. 5 through 8 a further process sequence for producing voids;

[0007]FIG. 9 a first example of a sensor according to the presentinvention;

[0008]FIGS. 10 through 12 further process steps for producing a secondexample of a sensor according to the present invention;

[0009]FIG. 13 a further example of a sensor according to the presentinvention; and

[0010]FIG. 14 a further sensor according to the present invention.

DETAILED DESCRIPTION

[0011] A process sequence elucidating the method of the presentinvention is shown in FIGS. 1 through 4. Shown in FIG. 1 is across-section of a silicon substrate 1, into which an opening 2 isintroduced. Opening 2 takes the form of a long, thin, blind hole, whichtypically has a diameter of less than 1 μm and extends more than 1 μminto the depth of silicon substrate 1. Silicon substrate 1 is, inparticular, a monocrystalline silicon substrate. Such openings may beproduced by reactive ion etching, i.e. irradiating the surface ofsilicon substrate 1 with ions of a gas, which form a gaseous chemicalcompound with the silicon material. Usually, the part of the surface ofsilicon substrate 1 that should not be etched is protected by a maskingof, for example, silicon oxide, silicon nitride, metals, or glasslayers. A purely ablative, plasma-etching method may also be used as analternative.

[0012] Silicon substrate 1, whose cross-section in shown in FIG. 1, isthen subjected to a temperature treatment. In this context, temperaturesat which silicon atoms can be rearranged, i.e. temperatures greater than900° C., are selected. For example, a temperature treatment of 1100° C.is particularly suitable. Such a temperature treatment is preferablycarried out in a hydrogen atmosphere, since, in this case, oxide formingon the surface of silicon 1 may be removed from the surface of silicon 1and from the walls of opening 2. The high temperatures increase themobility of the silicon atoms, so that a rearrangement occurs in suchmanner, that the surface area of the silicon is reduced. As can be seenin FIG. 2, the result of this is that the diameter of opening 2decreases in the upper region of opening 2, i.e. in the region very nearthe surface of silicon substrate 1, and a hollow forms in the lowerregion of opening 2. When this method is continued for a while, thesituation shown in FIG. 3 occurs, i.e. a slight depression is stillpresent on the surface of silicon substrate 1, while a void 3 is formedin the interior of silicon substrate 1. However, such a void 3 is onlyformed, when opening 2, as shown in FIG. 1, is sufficiently deep andsufficiently narrow. Otherwise, in order to minimize the surfacetension, it is energetically more favorable when only a depression 4 isformed. Consequently, opening 2 must be sufficiently deep, and thecross-sectional area must be sufficiently small. It is at leastnecessary for the depth of opening 2 in silicon substrate 1 to begreater than the diameter of opening 2 at the surface. In FIG. 3, aminimum state with regard to the surface area is not yet reached. Thesurface of silicon substrate 1 still has a depression 4, and void 3still has an oval shape. However, this state is further changed bycontinuing the temperature treatment, and a nearly spherical void 3 isthen formed, over which there is also no more depression 4. This stateis shown in FIG. 4.

[0013] Therefore, it is possible to produce a void 3 in a siliconsubstrate 1, by introducing an opening 2 and carrying out a subsequenttemperature treatment.

[0014] The method of the present invention is not limited tomonocrystalline silicon, but may equally be implemented in othersemiconductor materials, such as GaAs. In addition, polycrystallinesemiconductor material may also be used. Semiconductors have theadvantage that conductive and nonconductive regions necessary for themanufacturing of sensors may be produced by further processing steps.

[0015] When only hydrogen is trapped in the void, then an effectivevacuum is produced by a further temperature treatment, since thehydrogen easily diffuses out through the silicon. This is especially ofinterest for pressure sensors, since a reference vacuum is consequentlyproduced. Further temperature treatments are accomplished, for example,by introducing and heat-treating dopants.

[0016]FIGS. 5 through 8 show how this method may produce a membrane thatis situated over a void. Shown in FIG. 5 is a cross-section of siliconsubstrate 1, in which several openings 2 taking the form of narrow,deep, blind holes are introduced. A plan view of the substrate accordingto FIG. 5 is shown in FIG. 7. As can be seen in FIG. 7, several openings2 are spaced in close proximity to each other, the spacing of openings 2approximately corresponding to the diameter of openings 2. When FIGS. 5and 7 are used as a starting point and a temperature treatment iscarried out, silicon atoms are rearranged in each opening 2, as wasdescribed with regard to FIGS. 1 through 4. The result is a connected,large-area void 3, as is shown in FIG. 6 in a cross-section of siliconsubstrate 1. A membrane region 4, which is made up of a thin layer ofsilicon, is situated above areal void 3. When silicon substrate 1 is amonocrystalline silicon substrate, then this membrane 4 is formed, inturn, by monocrystalline silicon, since, during the rearrangement, thesilicon atoms position themselves at the proper crystal-lattice places.Therefore, the monocrystalline structure of silicon substrate 1 is alsomaintained in membrane region 4 over void 3. FIG. 8 shows a plan view,in which case it is clear that void 3 cannot be seen in a plan view.Therefore, areal void 3 represented in FIG. 8 may not be seen in theplan view but is nevertheless shown in FIG. 8, in order to give an ideaof how a void 3 is formed in the depth of the silicon substrate,starting out from visible openings 2 in FIG. 7.

[0017] In the configuration of openings 2, as is shown in FIGS. 5 and 7,there is a correlation between the diameter of openings 2, the spacingof openings 2, and the depth of openings 2. The deeper openings 2 areput into silicon substrate 1, the greater the distance may be betweenadjacent openings 2 in FIG. 7 in order to still produce a continuousvoid 3, as is shown in FIG. 8. If necessary, the exact size ratios ofthe diameter of openings 2, the spacing of openings 2 with respect toeach other, and the depth of openings 2 must be determinedexperimentally and may also be a function of further parameters, such asthe temperature of the temperature treatment, any introduced dopants,the composition of a protective gas during the temperature treatment,and the like.

[0018] However, in order to attain sensor patterns from the methoddescribed in FIGS. 1 through 8, further processing of silicon substrate1 is necessary.

[0019]FIG. 9 shows a first example of a sensor according to the presentinvention, which starts out from a silicon substrate 1, as isrepresented in FIGS. 6 and 8. Silicon substrate 1 has a void 3 and amembrane region 4 situated above it. Starting out from silicon substrate1, as is shown by way of example in FIGS. 6 through 8, an epitaxy layer11 is applied which covers the entire upper side of silicon substrate 1,including membrane region 4. Since silicon substrate 1 ismonocrystalline and the monocrystalline silicon structure is alsopresent in the region of membrane 4, epitaxy layer 11 grows in amonocrystalline manner. Typical thicknesses of such an epitaxy layer 11are on the order of several μm to several tens of μm. Dopants are thenintroduced on the upper side of epitaxy layer 11, using customarymethods. For example, doping zones 12 may be introduced forpiezoresistive resistor elements, which are then connected to contactopenings 14 of a passivation layer 15 by highly doped lead zones 13. Inthis context, piezoresistive resistor elements 12 are positioned to besituated in epitaxy layer 11 in the edge regions of void 3. Using highlydoped lead elements 13, electrical signals may then be tapped at contactopenings 14, via metallic conductor tracks (not shown). In particular,the electrical resistance of piezoresistive elements 13 may be measured.Because of their positioning relative to void 3, piezoresistive elements12 are in regions in which considerable mechanical stresses occur, incase epitaxy layer 11 and membrane region 4 deform above void 3. Suchdeformation may occur, for example, because the ambient pressuredeviates from the pressure trapped in void 3. Therefore, a device isprovided, which detects a change in the ambient pressure relative to thepressure in void 3, i.e. it is a pressure sensor. Using metallicconducting layers on the upper side of passivation layer 15, theelectrical signals of piezoresistive elements 12 may be supplied to anevaluation circuit 20, which is likewise formed in epitaxy layer 11 andsilicon substrate 1. For reasons of simplification, the metallicconductor tracks on the upper side of passivation layer 15 are notshown. In the same way, the electrical evaluation circuits are onlyindicated by diffusion zones 21, 22, and 23 and are by no meansequivalent to real circuit elements. Due to buried doping zone 21,dopant has already been introduced into the upper side of siliconsubstrate 1 prior to the deposition of epitaxy layer 11. Doping zones 22and 23 are customary doping zones introduced during the production ofcustomary semiconductor elements. In this context, processes are usedwhich are also used for producing piezoresistive elements 12 andhighly-doped leads 13. The method of the present invention for producingvoid 3 may easily be used with customary methods for producingsemiconductor patterns, so that both voids 3 and customary circuitelements 20 may be produced in one and the same process sequence.

[0020] An additional manufacturing process for a pressure sensor isshown in FIGS. 10, 11, and 12. However, in addition to the method stepsdescribed in FIGS. 1 through 8, dopant is also introduced into siliconsubstrate 1 before and after the production of void 3. In this context,one starts out from a homogeneously doped silicon substrate, e.g. ap-doped silicon substrate, in which an opposite type of doping 30, e.g.n-doping, is then introduced. Openings 2 are then introduced, as shownin FIGS. 5 through 7. The region in which openings 2 are situatedextends into both p-doped substrate 1 and introduced n-doping 30. Thedepth of openings 2 is less than the depth of doping 30, so that doping30 is still found under openings 2. This state is shown in FIG. 10a. Thetemperature treatment then produces a void 3, which extends into theinterior of substrate 1 and horizontally cuts through introducedn-doping 30, so that the silicon above and below void 3 is n-doped. Asit were, void 3 cuts through the doping region in the horizontaldirection. This produces upper doping 31 and lower doping 32. Byintroducing a re-doping zone 33 into the n-doped zones, i.e. byintroducing a large number of p-dopants, upper n-doping 31 and lowern-doping 32 may then be electrically insulated from each other. Shown inFIG. 10b is a cross-section of silicon substrate 1 produced in thismanner, where upper n-doping 31 is electrically insulated from lowern-doping 32 by void 3 and redoping zone 33. FIG. 11 shows a plan view ofFIG. 10b. As is apparent, redoping 33 is positioned in such a manner,that it is electrically situated between n-doping 32 and n-doping 31.Alternatively, redoping 33 may also be positioned in such a manner, thatit completely surrounds upper n-doping 31. In addition, FIGS. 10 and 11also show a doping, zone 21 for a buried doping zone, which is customaryfor the production of bipolar circuits.

[0021] Starting out from FIGS. 10 and 11, an n-doped epitaxy layer 11 isthen applied, in order to produce a sensor element. In this context,deep contacting areas 35 und 36, which are also n-doped, are introducedinto epitaxy layer 11. In this case, deep contacting area 35 ispositioned in such a manner, that upper n-doping 31 is electricallycontacted, and deep contacting area 36 is positioned in such a manner,that lower n-doping 32 is electrically contacted. P-doped insulatingrings 37 are produced around deep contacting area 36 and around uppern-doping 31 to provide mutual electrical insulation. A passivation layer15, into which contact openings 14 are introduced, is then applied tothe upper side again. Contact openings 14 are placed in such a manner,that deep contacting areas 35 are contacted by metallic surface filmsnot shown, so that an electrical surface connection may be made tocircuit elements 20, which are likewise formed in semiconductorsubstrate 1 and epitaxy layer 11. Semiconductor circuit elements 20 are,in turn, only schematically represented by buried doping zone 21 andfurther doping zones 22 und 23.

[0022] The device shown in FIG. 12 represents a capacitive pressuresensor. In the event of a pressure difference between void 3 and thesurroundings, epitaxy layer 11 and the region of semiconductor substrate1 situated above void 3 deform. This changes the distance between upperdoping zone 31 and lower doping zone 32. Since these two zones areelectrically insulated from each other, they form a plate-typecapacitor, whose capacitance is a function of the spacing of dopingzones 31 and 32. Deep contacting areas 35 and 36 allow this capacitanceto be detected by an appropriate evaluation circuit. The level ofdeformation of epitaxy layer 11 and semiconductor substrate 1 may beinferred by measuring the capacitance, and, in this manner, the ratio ofthe ambient pressure to the pressure in void 3 may be determined. Thecapacitive measuring principal is particularly advantageous, since it isespecially independent of temperature. In addition, the capacitances maybe evaluated in a particularly effective manner by circuits situated inthe immediate vicinity.

[0023] A further exemplary embodiment of a sensor according to thepresent invention is shown in FIG. 13. Using a substrate 1 representedin FIGS. 6 and 8 as a starting point, an epitaxy layer 11 is applied. Inthis context, a region above membrane 3 is provided with a high level ofdoping 50, so that epitaxy layer 11 is highly conductive in this region.In addition, high surface dopings 52 are introduced, which are used aselectrical leads to contact holes 14 in a passivation layer 15. Trenches51 are subsequently introduced by an etching process, which extends fromthe upper side of epitaxy layer 11 to void 3. In this manner, beamstructures 55 are produced, which may be geometrically designed to be,for example, movable by an acceleration parallel to the surface ofsubstrate 1. In addition, measures for insulating these beam structures55 among themselves and with respect to epitaxy layer 11 may also bedeveloped in edge regions not shown. In this manner, it is possible tomeasure capacitances between the beam structures and between beamstructures 55 and the rest of epitaxy layer 11, the capacitances being afunction of how much beam structures 55 are deformed. These capacitivesignals may then be transmitted, in turn, by metallized conductor tracksnot shown, to electronic circuits 20 also formed in epitaxy layer 11,via surface-doped conductive layers 52 and contact openings 14. In thismanner, a capacitive force sensor, e.g. an acceleration sensor, isproduced.

[0024] Shown in FIG. 14 is a further example of a sensor, which startsout from a substrate according to FIGS. 6 and 8. A movable element, inwhich trenches 51 extending to void 3 are introduced, is patterned outof an upper silicon layer, which is either formed out of only membranelayer 4, or made of a corresponding epitaxy layer 11. In the plan viewof silicon substrate 1 in FIG. 14, the boundaries of void 3 arerepresented by dotted line 62. Trenches 51 allow a seismic weight 71suspended from four beam elements 72 to be formed out of the uppersilicon layer. Piezoresistive elements 73 are situated on each of beamelements 72. These piezoresistive elements 73 allow the action of aforce, in particular an acceleration force acting on seismic weight 71,to be detected, for when a force acts on weight 71, suspension arms 72are deformed and corresponding changes in the resistance ofpiezoresistive elements 73 may be detected. In this case, both forcesperpendicular to substrate 1 and forces parallel to the surface of thesubstrate may be detected.

[0025] The advantage of the sensors shown in FIGS. 9 through 14 is thatthe sensor structures are all made of monocrystalline silicon.Therefore, piezoresistive resistor elements having high precision andlong-term durability may be introduced. In addition, movable elementsmade of monocrystalline silicon are of a particularly high quality andonly show small aging effects. In addition, the method of the presentinvention may be completely integrated with customary semiconductormanufacturing processes, so that both bipolar circuits and CMOS circuitsmay be integrated on the same substrate. In this manner, sensor elementsand semiconductor circuit elements may be jointly integrated on onesubstrate. Furthermore, only customary semiconductor manufacturingprocesses are used.

What is claimed is:
 1. A method for manufacturing micromechanicalsensors, in which openings (2) are introduced into a semiconductorsubstrate (1), and a temperature treatment is subsequently carried out,wherein the geometric dimensions of the openings (2) and the temperatureduration and time duration of the temperature treatment are selected insuch a manner, that a void (3) forms in the depth of the substrate (1).2. The method as recited in claim 1, wherein the openings (2) extendfrom an upper surface of the semiconductor substrate (1) into thesemiconductor substrate (1) to a depth, and the spacing of the sidewalls of the openings (2) is less than the depth of the openings (2). 3.The method as recited in claim 2, wherein the openings (2) at thesurface of the semiconductor substrate (1) are smaller than one μm in adirection and have a depth greater than 2 μm.
 4. The method as recitedin one of the preceding claims, wherein the temperature treatment iscarried out at temperatures greater than 900° C., and preferably greaterthan 1000° C.
 5. The method as recited in one of the preceding claims,wherein further processing steps are taken to form the sensors.
 6. Themethod as recited in claim 5, wherein, as a further process step, anepitaxy layer (11) is deposited on the surface of the semiconductorsubstrate (1).
 7. The method as recited in claim 5 or 6, wherein dopantsfor doping semiconductor material are introduced prior to or after thedeposition of the epitaxy layer (11).
 8. The method as recited in claim7, wherein piezoresistive elements (12, 73) are formed inmonocrystalline semiconductor material by dopants.
 9. The method asrecited in one of claims 5 through 8, wherein dopants are introducedinto the semiconductor substrate (1) prior to introducing the openings(2).
 10. A sensor element, which is manufactured according to one ofmethods 1 through 9, wherein an upper doping layer (31) is providedabove the void (3), and a lower doping layer (32) is provided below thevoid (3), the upper and lower doping layers being insulated from eachother by a p-n junction.
 11. A sensor, which is manufactured accordingto a method as recited in claims 1 through 9, wherein, above the void(3), trench structures (51) extending from an upper surface to the void(3) are introduced into the semiconductor.
 12. The sensor as recited inclaim 11, wherein beam structures (55), which are movable in a directionparallel to the surface of the substrate (1), are produced with the aidof the trenches (51).
 13. The sensor as recited in claim 12, wherein thebeam structures (55) have side walls, which are rendered conductive byintroducing dopants.